Parallel CRC Computation in FPGAs
نویسندگان
چکیده
This paper presents how to compute n-bit CRC checksums on FPGAs in parallel. For this task, a specialized logic minimization strategy is outlined. It achieves signiicantly better results than standard logic optimizers. For n 96, CRC designs with an n-bit I/O interface are poorly routable. However, for smaller I/O interfaces even a 128-bit CRC can be implemented.
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